From: tpa10@css.amdahl.com (Thomas P. Anderson) Subject: Re: Multi-Processor Architecture Date: 20 May 1993 18:52:30 GMT
In article <1993May18.193245.7423@mtu.edu>, tony@mtu.edu (Tony Dal Santo) writes:
|> Kelly Murray (kem@prl.ufl.edu) wrote:
|> > In article <1993May18.021425.7026@mtu.edu>, tony@mtu.edu (Tony Dal Santo) writes:
|> > |> While discussing kernels and multiprocessor machines, the question came up
|> > |> of whether the PC architecture would support multiple CPUs. I imagine
|> > |> this would work if you put another CPU and memory in a bus slot. Accessing
|> > |> "remote" memory over the bus would be slow, but usable. You may even be
|> > |> able to connect two buses together via a cable, but there may be length
|> > |> limitations. Or how about using the Local Bus? Or doesn't it allow a bus
|> > |> master in those slots? Hardware isn't my specialty. Come to think of
|> > |> it, I don't think I have a specialty.
|> > |>
|>
|> > I was hoping some of those "PC on a card" systems would allow you to plug
|> > multiple PC's into the bus and run them in parallel. Not possible. The
|> > existing PC bus technology won't support multiprocessors. The cheap and
|> > easy route is to use Ethernet to connect up a bunch of motherboards.
|> > Increase the bandwidth by using multiple Ethernet cards, or go with the
|> > more expensive 16mbit token ring network cards.
|>
|> I find it hard to believe that this isn't possible. I am probably being
|> naive, but here is my reasoning. Imagine a disk controller. It is
|> effectively a CPU with RAM and ROM. It can transfer (via DMA) to and from
|> system memory. It can cause interrupts.
|>
|> Now instead of a disk controller, imagine a 486 again with its own RAM
|> (say 8 meg) and [EP]ROMs. It should be able to communicate with the
|> "main" CPU again via DMA and interrupts. Using the EISA bus would make
|> this a LOT faster than ethernet.
|>
|> When doing DMA, how is this coordinated with the CPU? Is there any type
|> of guarantee that a CPU and a device won't be updating the same area of
|> memory? Can a "page" be locked? Is there some type of test-and-set bus
|> equivalent? Can anyone point me in the direction of the bus specs (both
|> EISA and Local Bus)?
|>
|> Thanks,
|> Tony Dal Santo
It's been a while, but I believe that locking IS available as that is how the
x87 processors share the bus with the x86s. As to the usage of DMA, it makes
perfect sense I believe the usage of IRQs is what keeps the main processor off
the bus while the DMA is going on.
Tom Anderson | Ex ignorantia ad sapientiam
Compatibility Software Products | e tenebris ad lucem!
tpa10@css.amdahl.com x63115 | - someone famous, i'm sure!